Hardware Description Languages (HDLs), such as the Very high-speed integrated circuit Hardware Description Language (VHDL) or Verilog are text-based approaches to digital logic design through behavioral and/or structural description of design elements. HDL can be used to design: (1) a programmable logic device (PLD), such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD); (2) a mask programmable device, such as a hardwired programmable gate array (PGA), application-specific standard product (ASSP) or application specific integrated circuit (ASIC); (3) a system formed from selected electronic hardware components; or (4) any other electronic device. The HDL-based design methodology requires the user to describe the behavior of a system, which can then be simulated to determine whether the design will function as desired. The design is then synthesized to create a logical network list (“netlist”) that can be implemented within a particular device.
As the complexity of design is rapidly increasing, a higher level of abstraction than a HDL is becoming more popular to design ICs. An example is a high level modeling system (HLMS). A HLMS is a software tool in which electronic designs can be described, simulated, and translated by machine into a design realization. An HLMS generally provides a mathematical representation of signals as compared to standard logic vectors in a HDL. The Xilinx System Generator tool for DSP is an example HLMS that runs within the MathWorks' Simulink and MATLAB environments.
In some instances, an HLMS is used to design and simulate integrated circuitry, where some circuit elements are described using HDL. For example, HDLs provide special constructs for designing ICs, including semantics for concurrency, reactivity, hardware style communication, and the like. As such, many ICs are designed using HDL, resulting in readily available HDL descriptions of circuit elements.
Typically, an IC design produced by an HLMS is implemented using a software program language, such as C, C++, or Java. IC designs inside the HLMS are constructed from software objects that are available in the language used to implement the HLMS. Software program languages differ from HDL in many respects, including syntax, semantics, data types, and system interface. As such, HDL descriptions of circuit elements cannot be used directly with the software program language environment of an HLMS, or the program language description of an IC produced by an HLMS.
Consequently, an HDL co-simulation process is conventionally employed when incorporating HDL descriptions of circuit elements within an IC design implemented using an HLMS. HDL co-simulation is a process whereby HDL descriptions of circuit elements are simulated using a separate stand-alone HDL simulator. The simulation results are forwarded to the HLMS using inter-process communication between the HLMS and the stand-alone HDL simulator. Such inter-process communication between two individual circuit design tools may be onerous. For example, HDL co-simulation requires the compilation of the HDL description every time the IC design is simulated within the HLMS. Furthermore, it is difficult to optimize an IC design produced by an HLMS when portions of the IC design are simulated using a stand-alone HDL simulator.
Therefore, there exists a need in the art for simulation of integrated circuitry within a high-level modeling system using HDL circuit descriptions without employing HDL co-simulation or other mechanisms requiring inter-process communication.